This document (last updated 2/9/96) hails from http://www.mips.com/r10k/T5_Intro.html
-- always reference the above link, for the most current, up-to-date version of this page.

MIPS R10000 (T5) Next Generation Technology

200MHz R10000 now shipping in SGI's Power Challenge 10000:


	SPECint95: 8.90		SPECfp95: 12.3	Peak
	SPECint95: 8.14		SPECfp95: 10.5	Base

Maximum performance of 200MHz R10000 (early hardware):


	SPECint95: 9*,		SPECfp95: 19* (early hardware)

275MHz R10000:(expected by end'96):


	SPECint95: 12*		SPECfp95: 24*

* (SPEC reporting regulations requires that figures marked * are classified as estimates, not measured).

Single chip superscaler RISC dataflow architecture
ANDES Advance Architecture (Architecture with Non-Sequential Dynamic Execution Scheduling).
Supports MIPS I, II, III, IV Instruction Set Architecture (ISA).
New Avalanche System Interface (up to 1.6GB/sec).
Improved SCache support (up to 16MB of SSRAM, up to 3.2GB/sec).
Improved multiprocessor support.
Excellent performance on previously-compiled R4XXX code.
Industry leading performance on real applications.
Designed for desktop and server systems.
Runs Windows NT and Unix operating systems.
Designed fo digital media network applications.

R10000, ANDES and Avalanche are trademarks of MIPS Technologies, Inc.

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